Zygoma::ia32::IOApicRedirection Class Reference

#include <ioapic.h>

List of all members.

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Detailed Description

An IO APIC redirection table entry.

One of these babies is used to define how to handle each of the 24 interrupt signals.

The IO APIC redirection table contains the following fields.

Destination Field (bits 56:63)

See Destnation Mode below for a description.

This field is read-write.

Interrupt Mask(bit 16)

Masks this particular interrupt signal when set.

This field is read-write.

Trigger Mode (bit 15)

Indicates the type of signal the triggers the interrupt. 1 is level sensitive and 0 is edge sensitive.

This field is read-write.

Remote IRR (bit 14)

This field is valid only if the Trigger Mode is 1. It is set when the Local APIC(s) acknowledge receipt of a level sensitive inetrrupt and cleared on EOI.

This field is read-only.

Interrupt Pin Polarity (bit 13)

0 is active-high, 1 is active-low.

The Intel documentation refers to this field as INTPOL. This field is read-write.

Delivery Status (bit 12)

0 is IDLE, 1 is PENDING.

The Intel documentation refers to this field as DELIVS. This field is read-only.

Destination mode (bit 11)

Determines the meaning of the Destination Field.

Physical Mode	0	Bits 0:4 of the Destination Field contain the Local APIC ID of the destination.
Logical Mode	1	Bits 0:8 of the Destination Field contain a bitmap (?) of the set of processors.

The Intel documentation refers to this field as DESTMOD. This field is read-write.

Delivery Mode (bits 8:10)

Specifies how the destination APIC should act on reception of the interrupt.

Fixed	0	Delivers the interrupt on the INTR pin of all processors listed in the destination. Can be edge or level delivery mode.
Lowest Priority	1	Delivers the interrupt on the INTR pin of the processor with the executing at the lowest priority among the processors listed in the destination. Can be edge or level delivery mode.
SMI	2	System Management Interrupt. Vector information is ignored but should be set to all zeros just in case. Required edge trigger mode delivery.
Reserved	3
NMI	4	Non-maskable Interrupt. Vector information is ignored but should be set to all zeros just in case. Required edge trigger mode delivery.
INIT	5	Initialization Interrupt. Asserts INIT signal for all processors listed in the destination which theoretically will force them to reset. Required edge trigger mode delivery.
Reserved	6
ExtINT	7	External Interrupt. Delivers the interrupt on the INTR pin of all processors listed in the destination as if it came from an Intel 8259A-compatible inetrrupt controller. Requires an edge trigger mode delivery.

The Intel documentation refers to this field as DELMOD. This field is read-write.

Interrupt Vector (bits 0:7)

The interrupt vector itself. Must be zero (see delivery mode) or a value between 0x10 and 0xfe.

The Intel documentation refers to this field as INTVEC. This field is read-write.

Public Attributes
u08	m_vector
u08	m_deliverMode:3
u08	m_destinationMode:1
u08	m_deliveryStatus:1
u08	m_pinPolarity:1
u08	m_remoteIRR:1
u08	m_triggerMode:1
u08	m_interruptMask:1
u08	m_reserved17:7
u08	m_reserved24
u08	m_reserved32
u08	m_reserved40
u08	m_reserved48
u08	m_destination

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Member Data Documentation

u08 Zygoma::ia32::IOApicRedirection::m_deliverMode

u08 Zygoma::ia32::IOApicRedirection::m_deliveryStatus

u08 Zygoma::ia32::IOApicRedirection::m_destination

u08 Zygoma::ia32::IOApicRedirection::m_destinationMode

u08 Zygoma::ia32::IOApicRedirection::m_interruptMask

u08 Zygoma::ia32::IOApicRedirection::m_pinPolarity

u08 Zygoma::ia32::IOApicRedirection::m_remoteIRR

u08 Zygoma::ia32::IOApicRedirection::m_reserved17

u08 Zygoma::ia32::IOApicRedirection::m_reserved24

u08 Zygoma::ia32::IOApicRedirection::m_reserved32

u08 Zygoma::ia32::IOApicRedirection::m_reserved40

u08 Zygoma::ia32::IOApicRedirection::m_reserved48

u08 Zygoma::ia32::IOApicRedirection::m_triggerMode

u08 Zygoma::ia32::IOApicRedirection::m_vector

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The documentation for this class was generated from the following file:

• ioapic.h

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