Fixed | 0 | Delivers the interrupt on the INTR pin of all processors listed in the destination. Can be edge or level delivery mode. |
Lowest Priority | 1 | Delivers the interrupt on the INTR pin of the processor with the executing at the lowest priority among the processors listed in the destination. Can be edge or level delivery mode. |
SMI | 2 | System Management Interrupt. Vector information is ignored but should be set to all zeros just in case. Required edge trigger mode delivery. |
Reserved | 3 | |
NMI | 4 | Non-maskable Interrupt. Vector information is ignored but should be set to all zeros just in case. Required edge trigger mode delivery. |
INIT | 5 | Initialization Interrupt. Asserts INIT signal for all processors listed in the destination which theoretically will force them to reset. Required edge trigger mode delivery. |
Reserved | 6 | |
ExtINT | 7 | External Interrupt. Delivers the interrupt on the INTR pin of all processors listed in the destination as if it came from an Intel 8259A-compatible inetrrupt controller. Requires an edge trigger mode delivery. |
The Intel documentation refers to this field as DELMOD. This field is read-write.