Intel Advanced Programmable Interrupt Controller
[Intel IA32 (32-bit) Architecture]

Collaboration diagram for Intel Advanced Programmable Interrupt Controller:

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Detailed Description

IA-32 systems handle interrupts through a kind of a coprocessor arrangement, something called an APIC (Advanced Programmable Interrupt Controller). There are at least 2 APICs: the IO APIC, which senses interrupt lines being pulled, and the local APIC, which is notified by the IO APIC and then in turn notifies the CPU via the NMI and INTR lines.

There is one local APIC per CPU. The number of IO APICs depends on the physical configuration of the hardware.

Memory Mapping

The APIC is a memory mapped device (using regular memory addresses rather than IO space).

All local APICs are mapped to the same address, with a base at 0x0fee00000. Since modern CPUs have these devices physically integrated, no actual bus signals are sent out when addressing the local APICs. Local APIC base addresses must be aligned on a 4K boundary.

The default IO APIC base address is 0xfec00000. Additional IO APIC base addresses are assigned in 4K incremenets, so a second IO APIC base address would be 0xfec01000. IO APIC base addresses must be aligned on a 1K bounday.

If an MP configuration table is provided, it may specify non-default locations for the local and IO APICs.

APIC Operating Modes

The APIC can be operated in one of three modes.

PIC Mode

bypasses the APIC, also known as PC/AT mode since it is identical to how that ancient hardware worked.

On hardware reset, this is the default initial operating mode.

To disable this mode, write 0x70 to IO port 0x22 to select the IMCR (interrupt mode control register), then write 0x01 to IO port 0x23 to force NMI and INTR signals through the APIC.

Some hardware may not implement PIC mode, so the IMCR will not exist. The IMCRP bit of the MP feature information byte indicates if the IMCR is present (and PIC mode is available).

Virtual Wire Mode

This looks like PIC mode to the CPU, but the APIC is really intercepting interrupt pulls. This is the mode MS-DOS runs in.

The IO APIC is not normally used in this mode, and it will work only in single-CPU configuration. It is possible to program the IO APIC to work in this mode, but again it's as a pass-through.

Symmetric IO Mode

For multiprocessor systems.

To switch to Symmetric IO Mode, write 0x01 to the IMCR (if enabled), and enable IO APIC redirection table entries (TBD).

This is the mode in which zygoma will operate. If unable to transition to this mode, the kernel should fail.

Files
file	apic.cpp
	Local Advanced Programmable Interrupt Controller.
file	apic.h
	Intel Advanced Programmable Interrupt Controller.
file	ioapic.h
	Intel 82093 I/O Advanced Programmable Interrupt Controller.
file	ioapic.cpp
	Advanced System Interrupt Controller.

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